At the present time, predominantly polished or epitaxially coated silicon wafers having a diameter of 300 mm are used for the most demanding applications in the electronics industry. Silicon wafers having a substrate diameter of 450 mm are in development.
However, the enlargement of the substrate diameter is accompanied by major, in some instances also totally new, hitherto unknown technical problems.
Many processing steps, whether they are of purely mechanical (sawing, grinding, lapping), chemical (etching, cleaning) or chemical-mechanical nature (polishing), and also the thermal processes (epitaxial coating, annealing), require thorough revision, in part also with regard to the machines used therefor and the working materials.
Semiconductor wafers, after being sliced from a single crystal (ingot) composed of semiconductor material, are processed further in a multiplicity of process steps. After the grinding, cleaning and etching steps, in accordance with the prior art, the surface of the semiconductor wafers is smoothed by one or a plurality of polishing steps.
Obtaining a sufficiently good edge geometry and the surface flatness (nanotopology) are particularly critical in the manufacture of semiconductor wafers.
The nanotopology is usually expressed as height fluctuation PV (=“peak to valley”), relative to square measurement windows having an area of 2 mm×2 mm.
The final nanotopology of a semiconductor wafer is generally produced by means of a polishing process.
In the case of single-side polishing (SSP), semiconductor wafers are held during processing on the rear side on a support plate by means of cement, a vacuum or by means of adhesion and are subjected to polishing on the other side.
In the case of double-side polishing (DSP), semiconductor wafers are inserted loosely into a thin carrier plate and are polished on the front and rear sides simultaneously in a “freely floating” manner between an upper and a lower polishing plate each covered with a polishing pad. This polishing method is effected with the supply of a polishing agent slurry, usually based on a silica sol.
The prior art likewise discloses polishing using fixedly bonded abrasives (“Fixed Abrasive Polishing”, FAP), wherein the semiconductor wafer is polished on a polishing pad which, in contrast to other polishing pads, contains an abrasive substance bonded in the polishing pad (“Fixed Abrasive” or FA pad). The German Patent Application DE 10 2007 035 266 A1 describes a method for polishing a substrate composed of silicon material, using FA pads.
After DSP or FAP, the front sides of the semiconductor wafers are generally polished in a haze-free manner. As is usually effected using a softer polishing pad with the aid of an alkaline polishing sol. In the literature, this step is often designated as chemical mechanical polishing (CMP). CMP methods are described, for example, in US 2002-0077039 and in US 2008-0305722.
By comparison with single-side polishing (SSP), simultaneous double-side polishing (DSP) of semiconductor wafers is not only more economic, but higher flatness with regard to the surfaces of the semiconductor wafers is obtained as well.
Double-side polishing is described, for example, in U.S. Pat. No. 3,691,694. A suitable double-side polishing machine is described in DE 100 07 390 A1. In accordance with one embodiment of double-side polishing as described in EP 0 208 315 B1, semiconductor wafers in carrier plates composed of metal or plastic, which have suitably dimensioned cutouts, are moved between two rotating polishing plates covered with a polishing pad in the presence of a polishing agent (polishing sol) on a path predetermined by the machine and process parameters and are thereby polished (in the literature, carrier plates are designated as “templates”).
The double-side polishing step is usually carried out using a polishing pad composed of homogeneous, porous polymer foam having a hardness of 60 to 90 (Shore A), as described for example in DE 100 04 578 C1, where it is also disclosed that the polishing pad adhering to the upper polishing plate is pervaded by a network of channels and the polishing pad adhering to the lower polishing plate has a smooth surface without such a texture. This measure is intended firstly to ensure a homogeneous distribution of the polishing agent used during polishing and secondly to prevent the semiconductor wafer from adhering to the upper polishing pad when the upper polishing plate is raised after polishing has finished.
The upper polishing pad comprises a regular chequered arrangement of channels having a segment size of 5 mm×5 mm to 50 mm×50 mm and a channel width and depth of 0.5 to 2 mm. This arrangement is used to effect polishing at a polishing pressure preferably of 0.1 to 0.3 bar. The silicon removal rate is preferably between 0.1 and 1.5 μm/min and particularly preferably between 0.4 and 0.9 μm/min.
However, a procedure in accordance with DE 100 04 578 C1 results in an asymmetrical polishing removal at the outer edge of the semiconductor wafer at the opposite sides (rear side and front side).
A further cause of locally different polishing removals in the case of double-side polishing in accordance with the prior art is the fact that abraded material (semiconductor material, for example silicon or silicon oxide), removed from the surfaces of the semiconductor wafers in the polishing process covers (deposits on) the polishing pad surfaces to in part different extents. In particular, the regions of the polishing pad surface which come into contact with the surfaces of the semiconductor wafers during the polishing process the most often statistically in a defined time period are covered with abraded material. A ring-shaped area with abraded material often forms on the polishing pad surface.
The formation of regions covered with abraded material on the polishing pad surface is additionally fostered by a non-uniform polishing agent distribution in the working gap between polishing pad and carrier plate.
The areas of the polishing pad which are covered with abraded material constitute regions in which the pad is altered in terms of its texture and in terms of its composition near the surface. These regions therefore have different properties with regard to the polishing result in comparison with the regions which are affected to a lesser extent or not at all by covering with abraded material.
As polishing pad covering increases, it becomes more and more difficult to control the polishing machines in such a way that flat wafers having good geometry values (GBIR, wafer shape, edge roll-off) are produced. Furthermore, it is necessary to reckon with an increase in the micro roughness (haze values) of the wafers. The risk of polishing scratches and increased LLS values on the polished wafer surfaces likewise increases in a similar manner.
Regular polishing pad conditioning that becomes necessary as a result reduces the lifetime of the polishing pads (wear) and additionally adversely impairs—on account of the mechanical action on the polishing pad and the associated change in the polishing pad (thickness, pad structure, . . . )—the wafer geometry and form.
A further cause of the non-uniform polishing removal is, inter alia, a polishing agent distribution effected non-uniformly on the polishing pad and, as a consequence thereof, a non-uniform wetting of the surfaces to be polished with polishing agent, or application of polishing agent to said surfaces.
In accordance with the prior art, the polishing agent distribution is effected by gravitational force and centrifugal force. The polishing agent is introduced from above into the working gap between polishing pad and carrier plate and flows on account of the gravitational force inter alia through the cutouts for the semiconductor wafers in the carrier plate also onto the lower polishing pad. In this case, the polishing agent distribution is fostered by the rotational movement of the carrier plates and of the polishing plates covered with the polishing pads.
The uniform polishing agent distribution is impeded by the carrier plate, in particular with regard to the polishing pad regions lying below the carrier plate. In order to improve the polishing agent distribution, US 2006-178089 A describes a carrier plate having a multiplicity of round openings through which the polishing agent reaches the lower polishing pad.
The teaching of EP 1 676 672 A1 includes improving the supply of polishing agent to the lower polishing plate by at least 15% of the area of the carrier plate being occupied by holes that provide for the polishing agent a passage to the lower polishing plate.
However, these additional “polishing agent cutout” in the circular carrier plates reduce the area moment of inertia thereof and, as a consequence thereof, also the resistance thereof to torsion. That is disadvantageous since the risk of carrier plate warping is thereby increased. The warping of the carrier plate can lead to pad damage, reduced pad lifetime, particle generation, polishing scratches through to wafer fracture and damage to the installation.
On account of the further increasing surface area in semiconductor wafers of future generations, for example having a diameter of 450 mm, the uniform polishing agent distribution (application of polishing agent) can be realized only to a limited extent during the polishing process in accordance with the prior art.